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1 pipelined processor architecture
Англо-русский толковый словарь терминов и сокращений по ВТ, Интернету и программированию. > pipelined processor architecture
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2 pipelined processor architecture
Программирование: конвейерная архитектура процессораУниверсальный англо-русский словарь > pipelined processor architecture
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3 pipelined architecture
= pipelined processor architectureконвейерная архитектура [процессора]Англо-русский толковый словарь терминов и сокращений по ВТ, Интернету и программированию. > pipelined architecture
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4 processor
процессор ( аппаратное устройство или обрабатывающая программа); узел обработки- airborne data processor
- airborne processor
- algorithm processor
- alterable processor
- ancillary control processor
- arithmetic processor
- array processor
- assembly language processor
- associative processor
- attached processor
- auxiliary processor
- back-end processor
- background job processor
- background processor
- basic processor
- batch-mode processor
- bit-slice processor
- bit-stream processor
- byte-slice processor
- center processor
- central data processor
- central processor
- command processor
- communications processor
- console command processor
- content-addressable processor
- control processor
- data communication processor
- data flow processor
- data interchange processor
- data link processor
- data processor
- database processor
- dead processor
- demand-paged processor
- diagnostic processor
- digital signal processor
- digital speech processor
- display processor
- distributed database processor
- dual processor - fast-Fourier-transform processor
- FFT processor
- file control processor
- file processor
- file revision processor
- flexible processor
- floating-point arithmetic processor
- floating-point processor
- front-end processor
- gateway processor
- general-purpose processor
- general-register processor
- geometric arithmetic parallel processor
- geometry processor
- graphic job processor
- graphics processor
- heterogeneous-element processor
- highly concurrent processor
- host processor
- host-language processor
- I/O processor
- idle processor
- image processor
- input/output processor
- instruction processor
- integrated array processor
- interface processor
- interruptable processor
- language processor
- language-specific processor
- large-scale processor
- linguistic processor
- local processor
- logic processor
- look-ahead processor
- loosely coupled processors
- maintenance processor
- master processor
- mathematical processor
- math processor
- matrix-vector processor
- message processor
- microprogrammable processor
- mid-range processor
- modular acoustic processor
- multipipeline processor
- multiunit processor
- nearby processor
- node processor
- non-neighbor processor
- nonsegmented processor
- N-pipe processor
- numeric processor
- off-line processor
- one-bit processor
- on-line processor
- optical matrix processor
- orthogonal processor
- out-of-order processor
- output test processor
- painting processor
- Pentium processor
- peripheral processor
- pipeline processor
- pipelined processor
- pixel processor
- programmed data processor
- queue processor
- quiescent processor
- real-time processor
- reference processor
- resource allocation processor
- RISC-based processor
- RISC-processor
- satellite processor
- scientific processor
- segmented processor
- self-dispatching processor
- sending processor
- service processor
- simulation processor
- single-cycle processor
- slave processor
- SMT processor
- soft architecture processor
- software processor
- specially designed processor
- speech processor
- speech-synthesis processor
- stand-alone processor
- stochastic processor
- support processor
- system processor
- systolic processor
- terminal processor
- test result processor
- test-and-repair processor
- text processor
- tightly coupled processors
- transform processor
- uncooperative processor
- vector processor
- video-display processor
- viewing processor
- virtual processor
- VLSI array processor
- voice processor
- wavefront array processor - word-oriented processorEnglish-Russian dictionary of computer science and programming > processor
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5 architecture
1) структура; конфигурация; конструкция2) вчт архитектура•- bit-addressable architecture
- bit-slice architecture
- boundary scan architecture - bus architecture
- bus structured architecture
- chip architecture
- client-server architecture
- closed architecture - computer family architecture
- connectionist architecture
- data bus architecture
- data flow architecture
- defense-in-depth security architecture
- die architecture
- digital network architecture - dynamic power management architecture
- dynamic scalable architecture
- engagement architecture - firmware architecture
- hardware architecture
- Harvard architecture
- high-performance computer architecture
- hub architecture
- industry standard architecture
- linear addressing architecture
- machine check architecture
- medium control architecture
- micro channel architecture
- MIMD architecture
- MISD architecture
- modular architecture
- multi-issue architecture
- multiple-instruction multiple-data architecture
- multiple-instruction single-data architecture
- multiprocessor architecture
- multi-tier architecture
- network architecture
- neural network architecture - pipelined architecture
- Princeton architecture
- problem-oriented architecture
- process architecture
- PS/2 architecture - security architecture
- segmented addressing architecture
- segmented memory architecture
- serial storage architecture
- shading architecture
- shared memory architecture - single-instruction multiple-data architecture
- single-instruction single-data architecture
- SISD architecture
- slice architecture
- software architecture
- stack architecture
- stack-based architecture
- superpipelined architecture - systolic array architecture - tree architecture
- tree-and-branch architecture - unified memory architecture
- very long instruction word architecture
- virtual architecture - von Neumann architecture -
6 architecture
1) структура; конфигурация; конструкция2) вчт. архитектура•- bit-addressable architecture
- bit-slice architecture
- boundary scan architecture
- broadband network architecture
- bubble chip architecture
- bus architecture
- bus structured architecture
- chip architecture
- client-server architecture
- closed architecture
- common object request brokers architecture
- computer architecture
- computer family architecture
- connectionist architecture
- data bus architecture
- data flow architecture
- defense-in-depth security architecture
- die architecture
- digital network architecture
- distributed enterprise management architecture
- document content architecture
- document interchange architecture
- domain architecture
- dynamic power management architecture
- dynamic scalable architecture
- engagement architecture
- enhanced industry standard architecture
- extensible architecture
- final-form-text document content architecture
- firewall architecture
- firmware architecture
- hardware architecture
- Harvard architecture
- high-performance computer architecture
- hub architecture
- industry standard architecture
- linear addressing architecture
- machine check architecture
- medium control architecture
- micro channel architecture
- MIMD architecture
- MISD architecture
- modular architecture
- multi-issue architecture
- multiple-instruction multiple-data architecture
- multiple-instruction single-data architecture
- multiprocessor architecture
- multi-tier architecture
- network architecture
- neural network architecture
- office document architecture
- office document management architecture
- open architecture
- open document architecture
- open document management architecture
- open network architecture
- organizational architecture
- pipelined architecture
- Princeton architecture
- problem-oriented architecture
- process architecture
- PS/2 architecture
- revisable-form-text document content architecture
- scalable processor architecture
- security architecture
- segmented addressing architecture
- segmented memory architecture
- serial storage architecture
- shading architecture
- shared memory architecture
- signal computing system architecture
- SIMD architecture
- single-instruction multiple-data architecture
- single-instruction single-data architecture
- SISD architecture
- slice architecture
- software architecture
- stack architecture
- stack-based architecture
- superpipelined architecture
- systems application architecture
- systems monitor architecture
- systems network architecture
- systolic architecture
- systolic array architecture
- Texas Instruments graphics architecture
- three-tier architecture
- tree architecture
- tree-and-branch architecture
- twin-bank memory architecture
- two-level cache architecture
- unified memory architecture
- very long instruction word architecture
- virtual architecture
- virtual intelligent storage architecture
- VLIW architecture
- von Neumann architecture
- Windows open services architectureThe New English-Russian Dictionary of Radio-electronics > architecture
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7 pipeline processor
= pipelined processor; = pipelined CPUконвейерный процессор, процессор с конвейерной обработкой данных, процессор с конвейерной архитектуройАнгло-русский толковый словарь терминов и сокращений по ВТ, Интернету и программированию. > pipeline processor
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8 конвейерная архитектура процессора
Programming: pipelined processor architectureУниверсальный русско-английский словарь > конвейерная архитектура процессора
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9 pipeline
1) (см. тж. instruction pipeline, processor pipeline) - конвейер"сборочная линия" - цепочка параллельно работающих исполнительных устройств центрального процессора, на которой обработка команд разбивается на ряд небольших шагов, стадий или ступеней, выполняемых за один такт. Конвейер организован таким образом, что выходные данные одного устройства поступают на вход другого. Число стадий называется длиной конвейера. Использование конвейера позволяет начать исполнение следующей машинной команды в одном блоке до завершения предыдущей, т. е. с перекрытием по времени (различные стадии нескольких команд выполняются ЦП параллельно). Какова длина конвейера, столько команд одновременно он и может обрабатывать - и в идеале конвейеризация обеспечивает выигрыш в производительности (по сравнению с неконвейерными ЦП, non-pipelined processor), соответствующий числу ступеней конвейера. В современных процессорах конвейеры имеют длину до 20 стадий (Pentium 4). Однако параллельная обработка команд возможна не всегда, так как в программе часто встречаются команды условных переходов и ситуации, когда для исполнения команды требуется результат предшествующей команды. В таких случаях, чтобы предотвратить перезагрузку конвейера (см. pipeline break), применяются более сложные процессы: упреждающая обработка (предсказание переходов, branch prediction) или изменение порядка исполнения команд (out-of-order execution).The pipeline must be flushed before the CPU can respond to an interrupt. — Конвейер должен быть очищен перед тем как ЦП сможет реагировать на прерывание см. тж. balanced pipeline, branch delay slot, control-flow pipeline, execute phase, graphics pipeline, instruction pipeline, load delay slot, machine language, multipipeline processor, pipeline bubble, pipelined application, pipelined architecture, pipeline depth, pipeline diagram, pipeline error, pipeline processing, pipeline processor, pipeline scheduling, pipeline stall, stage, superpipelined, superscalar architecture, unbalanced pipeline
2) конвейеризировать, применять конвейерVector processors pipeline and parallelize the operations on the individual elements of a vector. — Векторные процессоры производят распараллеливание и конвейеризацию операций над индивидуальными элементами вектора см. тж. pipelining
3) конвейерныйАнгло-русский толковый словарь терминов и сокращений по ВТ, Интернету и программированию. > pipeline
См. также в других словарях:
Architecture MIPS — MIPS I R2000 • R3000 MIPS II R6000 MIPS III R4000 • R4200 • R4600 … Wikipédia en Français
Hazard (computer architecture) — Hazards are problems with the instruction pipeline in central processing unit (CPU) microarchitectures that potentially result in incorrect computation. There are typically three types of hazards: data hazards structural hazards control hazards… … Wikipedia
MIPS architecture — MIPS (originally an acronym for Microprocessor without Interlocked Pipeline Stages) is a RISC microprocessor architecture developed by MIPS Technologies. As of|1999|alt=By the late 1990s it was estimated that one in three RISC chips produced were … Wikipedia
Decoupled architecture — In computer science, a decoupled architecture is a processor with out of order execution that separates the fetch and decode stages from the execute stage in a pipelined processor by using a buffer. The buffer s purpose is to partition the memory … Wikipedia
Digital signal processor — A Digital Signal Processor chip found in a guitar effects unit. A digital signal processor (DSP) is a specialized microprocessor with an architecture optimized for the fast operational needs of digital signal processing.[1] … Wikipedia
Transport triggered architecture — The transport triggered architecture (TTA) is an application specific instruction set processor ( ASIP ) architecture template that allows easy customization of microprocessor designs. The basic idea of transport triggering is to allow programs… … Wikipedia
Vector processor — A vector processor, or array processor, is a CPU design where the instruction set includes operations that can perform mathematical operations on multiple data elements simultaneously. This is in contrast to a scalar processor which handles one… … Wikipedia
Instruction pipeline — Pipelining redirects here. For HTTP pipelining, see HTTP pipelining. Basic five stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back). In the fourth clock… … Wikipedia
Конвейер (процессоры)/Перевод — Пожалуйста, не удаляйте эту статью! В данный момент в ней идет работа по переводу основной английской версии для замены кошмарной русской. После завершения работы я объединю получившуюся статью с имеющейся русской версией. Простой пятиуровневый… … Википедия
Parallel computing — Programming paradigms Agent oriented Automata based Component based Flow based Pipelined Concatenative Concurrent computing … Wikipedia
Reduced instruction set computer — The acronym RISC (pronounced risk ), for reduced instruction set computing, represents a CPU design strategy emphasizing the insight that simplified instructions which do less may still provide for higher performance if this simplicity can be… … Wikipedia
